What you'll be doing:
Learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and verification engineers.
Define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.
Define the implementation of debug capabilities to support performance validation and improvements
Understand our system requirement and help define the POR of our switch product line.
Face the most challenging Full-Chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
Work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
Thoroughly understand Ethernet, InfiniBand and NvLink protocols.
What we need to see:
B.Sc. in Electrical Engineering from a known university.
Excellent grades.
5+ years of experience in ASIC design/uarch/arch/performance.
At least 4 years of hands on experience in writing Verilog/VHDL.
Strong analytic capabilities, and passion for solving logical issues.
Strong debug skills.
Ability to drive complex activities involving many interfaces and teams.
Good communications skill.
Ways to stand out from the crowd:
Knowledge in switching fabrics with strict performance requirements. (Networking, SOC connectivity, etc).
Experience as an HW-architect.
Familiar with working on large high-end ASICs.
Experience in performance improvements in ASIC.
