About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Own the chip development and execution. Be accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, planning and tracking.
Coordinate the work of different disciplines, such as design, verification, and test to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project – Technical Program Manager (TPM), design verification lead, Physical Design (PD) lead, Design for Testing lead, design lead and architecture team to make execution decisions and drive the development process.
Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures.
Lead the project development with excellent quality and address issues throughout the design and implementation phases.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Own the chip development and execution. Be accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, planning and tracking.
Coordinate the work of different disciplines, such as design, verification, and test to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project – Technical Program Manager (TPM), design verification lead, Physical Design (PD) lead, Design for Testing lead, design lead and architecture team to make execution decisions and drive the development process.
Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures.
Lead the project development with excellent quality and address issues throughout the design and implementation phases.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHDL language.
Experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.
Experience working with high speed, lower power design.
Experience in leading chip development projects and teams.
Preferred qualifications:
Master's degree or PhD in Engineering.
Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
Knowledge of advanced high performance CPU design and architecture.
Ability to motivate and focus large collaborative teams to achieve testing goals.
Excellent communication and facilitation skills.
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHDL language.
Experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.
Experience working with high speed, lower power design.
Experience in leading chip development projects and teams.
Preferred qualifications:
Master's degree or PhD in Engineering.
Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
Knowledge of advanced high performance CPU design and architecture.
Ability to motivate and focus large collaborative teams to achieve testing goals.
Excellent communication and facilitation skills.
This position is open to all candidates.
