looking for a best-in-class STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
Be in charge of full chip level STA convergence from early stages to signoff.
Take part in Full Chip floor plan design and Netlist creation with aim to optimize timing convergence and work efficiency.
Define and optimize, together with CAD, STA signoff flows and methodologies.
Digital Partitions' and analog IPs' timing integration, giving feedback and driving convergence.
Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including optimizing them for runtime and efficiency.
What you will be doing:
Be in charge of full chip level STA convergence from early stages to signoff.
Take part in Full Chip floor plan design and Netlist creation with aim to optimize timing convergence and work efficiency.
Define and optimize, together with CAD, STA signoff flows and methodologies.
Digital Partitions' and analog IPs' timing integration, giving feedback and driving convergence.
Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including optimizing them for runtime and efficiency.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
3+ years of experience in physical design and STA
Proven experience in RTL2GDS and STA flows and methodologies.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) and timing signoff (Primetime).
Great teammate.
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
3+ years of experience in physical design and STA
Proven experience in RTL2GDS and STA flows and methodologies.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) and timing signoff (Primetime).
Great teammate.
This position is open to all candidates.
