About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do – from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the System on a Chip (SoC)/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and Application-specific integrated circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC level verification.
Communicate and work with multi-disciplined and multi-site teams.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do – from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the System on a Chip (SoC)/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and Application-specific integrated circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or SystemVerilog
Experience with reasoning synthesis techniques to optimize RTL code, performance and power with low-power design techniques.
Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).
Experience in reasoning design and debug with Design Verification (DV).
Preferred qualifications:
Experience in coding languages like Python or Perl.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Knowledge of System-on-a-Chip (SoC) architecture.
Knowledge of PCIe, UCIe, DDR, AXI or ARM processors.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or SystemVerilog
Experience with reasoning synthesis techniques to optimize RTL code, performance and power with low-power design techniques.
Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).
Experience in reasoning design and debug with Design Verification (DV).
Preferred qualifications:
Experience in coding languages like Python or Perl.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Knowledge of System-on-a-Chip (SoC) architecture.
Knowledge of PCIe, UCIe, DDR, AXI or ARM processors.
This position is open to all candidates.
